1

9/13

Course Introduction & Logistics - by TA [slides]

(Instructor away at UbiComp)

Chap. 1.1

2

9/ 20

Introduction (1) [slides]

• Why and What is this course?
• What is a computer?
• Below your program
• Under the Covers
• Digital Binary Systems

Chap. 1.1~1.5

3

9/27

No class (due to typhoon)

4

10/4

Introduction (2)

• Performance
• The Power Wall
• The Switch from Uniprocessors to Multiprocessors

Instructions: Language of the Computer (1) [slides]

• Operations and Operands of the Computer Hardware
• Signed and Unsigned Numbers
• Representing Instructions in the Computer

Chap. 1.6~1.11 w/o 1.9
Chap. 2.1 ~2.6

5

10/11

Instructions: Language of the Computer (2)

• Logical Operations
• Instructions for Making Decisions
• Supporting Procedures
• Communicating with People
• MIPS Addressing
• Translating and Startinga Program
• Arrays vs. Pointers

Chap. 2.6~2.18 w/o 2.10, 2.13~16

6

10/18

How to Program? - by TA [slides]

Chap. 2, A.9 
MIPS32 Simulator: SPIM

7

10/25

Arithmetic for Computers [slides]

• Addition and Subtraction
• Gate Logic and K-Map Method
• Constructing a Basic Arithmetic Logic Unit
• Multiplication and Division
• Floating Point

Chap. 3.1~3.10 w/o 3.7
The basics of logic design

8

11/1

The Processor (1) [slides]

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme

Chap. 4.1~4.4
Mapping Control to Hardware

9

11/8

Midterm exam

10

11/15

No class (NTU Anniversary Celebration)

11

11/22

The Processor (2)

• An Overview of Pipelining
• Pipelined Datapath and Control

Chap. 4.5~4.6

12

11/29

The Processor (3)

• Data Hazards: Forwarding versus Stalling
• Control Hazards
• 
  

Chap. 4.7~4.9

13

12/6

Processor (4)

• Exception
• Parallelism via Instructions

Chap. 4.10~4.15 w/o 4.11~4.13

14

12/13

Large and Fast: Exploiting Memory Hierarchy (1) [slides]

• Introduction
• Memory Technologies
• The Basics of Caches

Chap. 5.1~5.3

15

12/20

Large and Fast: Exploiting Memory Hierarchy (2)

• Measuring and Improving Cache Performance
• Dependable Memory
• Virtual Machines

Chap. 5.4~5.6 

16

12/27

Large and Fast: Exploiting Memory Hierarchy (3)

• Virtual Memory
• A Common Framework for Memory Hierarchies
• Using A Finite State Machine to Control A Simple Cache

Embedded Processing Computers [slides]

Chap. 5.7~5.15 w/o Chap. 5.10~5.14

17

1/3

Parallel Processors from Client to Cloud [slides]

• Introduction
• The Difficulty of Creating Parallel Processing Programs
• SISD, MIMD, SIMD, SPMD, and Vector
• Introduction to Graphics Processing Units
• Fallacies and Pitfalls

Chap. 6.1~6.3, 6.6, and 6.13 

18

1/10

Final exam